The working principle of a DRAM
Dynamic random access memory (DRAM) contains an integrated circuit where each bit of data is stored in a separate capacitor. This capacitor charge should be refreshed within intervals to prevent it from fading due to charge leak. DRAM has advantages over the other modules due to its simplicity as it has only one transistor and a capacitor that is required per bit. Thus due to all these features DRAM reaches high density.
DRAM is arranged in a square array of one capacitor and transistor per cell. There are long lines that connect each row of cells in the module which is known as word lines. This works under the principle of positive feedback and there are several steps involved to read a column bit. This mechanism is influenced by ‘+’ and ‘-’ charges giving a complex type of reaction for both reading and writing of data. It is just the type of signal transfer between rows and columns. Since periodic refresh is necessary in DRAMs, refresh logic is used here as an external bit is used in the chip for refresh.
Memory timing is also an important criterion since it comes under Random access memory, it is volatile and all the stored information is lost when power is off. Thus many numbers are required for the DRAM operation. Packaging of DRAMs is also complex. DRAM is produced as integrated circuits (ICs) which are bonded and mounted onto plastic packages incorporated with metal pins for connection to their respective control signals and buses.
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